This, in turn, means having to go back to the page table structures when references are made to virtual addresses outside the scope of a small page whose translation has been cached. If small pages are used, more TLB entries are needed for the same range of virtual addresses, thus increasing recycling of entries as new virtual addresses require translation. This advantage exists because the first reference to any byte within a large page will cause the hardware’s translation look-aside buffer (TLB, described in a later section) to have in its cache the information necessary to translate references to any other byte within the large page. The primary advantage of large pages is speed of address translation for references to other data within the large page. Additionally, recent 圆4 processors support a size of 1 GB for large pages, but Windows does not use this feature. Windows on Itanium uses 8 KB and 16 MB for small and large pages, respectively, as a result of performance tests that confirmed these values as optimal.
IA64 | 8 KB | 16 MB | 2,048 Note IA64 processors support a variety of dynamically configurable page sizes, from 4 KB up to 256 MB. Architecture | Small Page Size | Large Page Size | Small Pages per Large Page
